1. Field of the Invention
This invention relates to shift register latch (SRL) arrangements for use in digital computers and the like and, more particularly, to a structure of an SRL arrangement for use in such systems to render it operable to fully test a specific type of combinational logic circuit producing complementary outputs such as a differential cascode voltage switch (DCVS) circuit.
2. Description of the Prior Art
DCVS is a circuit scheme recently developed for CMOS type devices, which not only provides high functional density and excellent performance characteristics but also has the unique property of inherent testability due to the presence of a pair of complementary outputs from every logic tree. This type of circuit is disclosed by Heller et al in a technical paper entitled "Cascode Voltage Switch Logic Family - A Differential CMOS Logic Family" appearing in Digest of Proceedings of IEEE International Solid-State Circuits Conference, Vol. 27, San Francisco (February 1984), pp. 16-17.
A typical DCVS circuit is partitioned into any number of basic building blocks called logic modules, each consisting of a logic tree and an associated buffer and precharge circuit. The buffer and precharge circuits are generally identical but the internal structure of the logic trees may be different depending on which logical function each logic tree is designed to represent. The DCVS circuit relies upon the presence of complementary signals at all points. Each primary input has complement and true versions, respectively. The tree outputs of a logic module, including the logic tree, are complement and true versions of the same logic signal. The inputs to the logic trees are either the complementary versions of the primary inputs or the complementary versions of the tree outputs of different logic trees.
For further details of the rules governing logical behavior of these modules, reference should be made to copending U.S. patent application Ser. No. 709,612, filed Mar. 8, 1985 by Z. Barzilai et al and assigned to the assignee of this invention.
DCVS circuits have many advantages. All logic functions can be implemented either by adequately interconnecting differential pairs of NMOS switches in a logic tree or by connecting its complementary tree outputs to other logic trees as their complementary inputs to thereby form a more powerful DCVS circuit comprising a group of logic modules. In the latter case, such a DCVS circuit may be formed as a combinational logic circuit which has multiple pairs of complementary inputs and multiple pairs of complementary outputs. Another important point is that, under normal operation for any combination of complementary input signals, a DCVS circuit should be double rail in nature, i.e., each logic module of the DCVS circuit in this case produces a pair of complementary outputs indicative of a result of the function it implements.
In order to alleviate the problems in testing aforesaid DCVS circuits of large scale integration (LSI) type, it has been proposed to incorporate shift register latches (SRLs) into DCVS designs in accordance with the existing "level sensitive scan design" or LSSD scheme. The latter scheme is fully described in a technical article by E. B. Eichelberger et al entitled "A Logic Design Structure for LSI Testability" appearing in Proceedings of 14th Design Automation Conference, June 1977, pp. 462-468.
In this prior approach, only a single tree output from the DCVS circuit is observed by latching it into the SRLs. Unfortunately, most manufacturing defects in a DCVS circuit, which may be modeled as single stuck-at faults as fully discussed in the above cited copending patent application, cause the true and complement tree outputs from the DCVS circuit not to be complements of each other. Therefore, the problem with this prior approach is the loss of observability points when testing for manufacturing defects.
Further, in a recent technical article by J. B. Hickson et al entitled "Testing Scheme for Differential Cascode Voltage Switch Circuits" appearing in IBM Technical Disclosure Bulletin, Vol. 27, No. 10B, Mar. 1985, pp. 6148-6152, there is described a testing scheme for enhancing observability of a DCVS circuit by placing an exclusive OR circuit at the output of every DCVS logic tree and by detecting whether its output value is in a legal state. However, the testing scheme is a big departure from the existing LSSD scheme and requires a substantial overhead in that there is provided a single exclusive OR circuit for each DCVS logic tree. Further, the testing scheme requires a sophisticated hierarchical wiring arrangement for certain error flag lines to ensure proper signal strengths.